Samsung Foundry May Look to the Take Lead in 2nm Race as TSMC Faces Challenges
TSMC may be world’s largest semiconductor foundry at the moment, but this year hasn’t been the best for them, particularly in the N3 segment. The company almost fully allocated it’s N3 production line to Apple for the upcoming A17 Bionic and M3, leaving the rest to look for other options.
Initially, TSMC had 10% 3nm lines reserved for Intel’s Arrow Lake processors, but design delays led to the company postponing their orders, which meant that other fabless companies such as Qualcomm, and AMD had to look towards Samsung Foundry for this year. Due to this, TSMC’s 3nm production has significantly dropped below average, moving from 80,000 units per month to ~50,000.
In July, it was even reported that Samsung has achieved a better yield than TSMC, and had a lower 3nm production price per wafer, which was a win-win for both sides. However, for TSMC, this is bad news, since Samsung may look to capitalize on their tight schedule, and try and win back lost clients from previous 5nm and 4nm.
Qualcomm is even considering outsourcing all of Snapdragon 8 Gen 4 orders to Samsung Foundry instead of taking a hybrid approach (not set in stone, as of now). See, both Samsung and TSMC start 2nm production in 2025, and every foundry player will be looking to go for the GAA (Gate All Around) transistor solution. The advantage Samsung has here is that they’ve already implemented this architecture in SF3 (3nm).
The expected numbers for 2nm mobile application processors had been announced earlier this year, and those are a completely different story. From the graphs down below (courtesy of Gadget Seoul, via Revegnus) it can clearly be seen how TSMC just has that slightest of edge in performance, but SF2 seems to be a more efficient solution.
The performance and power gap for both the foundries is really huge, which is a good thing considering how we can expect better performance and battery, both at the same time. However, this will surely put the clients in a bit of a dilemma, and it’ll ultimately come down to company preferences.
Keep in mind that other foundries like Intel and Rapidus have plans to offer 2nm mobile APs, but they haven’t made their schedule public, as of this writing.
As for the reason for such a huge performance bump, well, 2nm will be the node where foundries will use GAAFET transistors (like mentioned above), and will make use of backside power delivery solutions, which simply improves performance while minimizing power usage.
TSMC’s initial N2 manufacturing process, which was introduced last year, will be the foundry’s first node to use gate-all-around (GAAFET) transistors, which TSMC is calling Nanosheet transistors. GAAFET’s advantages over current FinFET transistors includes lowered leakage current (as gates are present on all four sides of the channel), as well as the ability to adjust channel width for higher performance or lower power consumption.
When introducing this technology last year, TSMC said that it would enhance transistor performance by 10% to 15% with the same power and complexity, or reduce power consumption by 25% to 30% at the same clock and transistor count. The company also says that N2 will offer ‘mixed’ chip densities of over 15% greater than N3E, which is an increase from the 10% density increase announced last year.
Anand Tech – TSMC Outlines 2nm Plans
At the end however, most clients will move to where they find better pricing and yields, alongside stable output. This is all we know for now, but rest assured that we will keep you updated as new information becomes available.
