According to TheElec, the ring is in advanced development as of now, and since the design (as of now) is simply too big for commercial use, Samsung is looking to tone down the dimensions a bit before moving to mass production.

The ring will apparently come in a single model, however, there will be four sizes available for different finger sizes. In addition to this, it is possible that the ring may be delayed until the first quarter of 2025. However, if it isn’t, the release of Samsung’s sixth-gen foldables may be delayed to launch alongside the ring altogether.

Not only that, but the Samsung Smart Ring will allegedly have better health tracking sensors than Samsung’s Smart Watch. Perhaps something similar to the Pixel Watch 2‘s multipath heart rate sensor; however, reducing the size would be challenging given how a lot of additional features will also be incorporated within the watch which will have to be cut down. Additionally, it will come equipped with ECG and PPG sensors.

Considering that Samsung will require medical approval for these health tracking sensors, which is mostly the primary objective of this ring, it is possible that the release itself may experience delays beyond the initial announcement. We also reported last month on the possibility of the watch being named ‘Curio,’ although this could merely be a codename for Samsung’s smart ring project.

At this moment, even after a lot of information has come to light, it is unclear why Samsung is keeping the smart ring project under wraps, but it’s possible that the company is still ironing out the details. See, smart rings are a relatively new product category, and there are still some challenges to overcome to bring them to commercial markets.

Samsung undoubtedly makes some of the best WearOS watches in the market, and this transition to a smaller form factor will bring about its own challenges. However, since the smart ring market isn’t populated with all sorts of companies, it’s possible that Samsung might just have a little bit of an edge after its first product launch.

With companies such as Oura running the same race for almost a decade now, Samsung might have problems competing at the start, but that is exactly what we want to see—something new and innovative in the smallest form factor.

This is all we know for now, but rest assured that we will keep you updated as new information becomes available.

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Arrow Lake, Up to 24 Cores with no Hyperthreading & RUs

Starting off with Arrow Lake, which is Intel’s first generation on the LGA 1851 platform, MLID claims that Arrow Lake will feature up to 24 cores. This is similar to Raptor Lake, and Raptor Lake Refresh, though there are two extra LPE cores, but their inclusion is negligible.

Furthermore, Arrow Lake cuts off Hyperthreading and does not use Rentable Units (RUs). You can read our detailed article regarding Rentable Units here. The single-core uplift is expected to be 25%, with multi-core still undecided, given how Arrow Lake does not have hyperthreading.

Arrow Lake is based on TSMC’s N3B node, with some variants built using Intel’s own 20A process. The start of LGA-1851 could slip into 2025, as Arrow Lake is targeting a late 2024 launch.

Arrow Lake Refresh, Same Architecture but With 40 Cores

In early 2025, Intel will launch Lunar Lake based on N3B which is meant for power-efficient laptops. It is the spiritual successor to Lakefield and the Tiger Lake-U series of CPUs.

In the second half of 2025, 1 year after Arrow Lake, Intel will reinstate the lineup with the leaked 40-Core SKU. It is very similar to how Raptor Lake Refresh and Raptor Lake work in tandem to pave way for the next-big architecture, in this case, Nova Lake.

ARL-R could be almost 50% faster in multi-threaded workloads due to its insanely high core-counts. Sadly for Intel, it will launch next to Zen6. This is kind of similar to if Raptor Lake Refresh launched side by side with Zen5. That would have an absolute bloodbath for Team Blue.

Panther Lake, New Architecture but Reserved for Laptops

Panther Lake is the new Meteor Lake, seeing how Intel is repeating its strategy. Arrow Lake is the big architecture, Arrow Lake Refresh follows up. The next major overhaul comes in the form of a mobile-only series (Panther Lake), serving as a test run for its desktop counterpart (Nova Lake).

By the start of 2026, Intel will unveil Panther Lake which uses the new Cougar Cove P-Cores and Darkmont E-Cores. It apparently introduces a new tile layout and is exclusive to the laptop segment.

Speaking of Cougar Cove, MLID reports that Cougar Cove might not feature RUs as well. In fact, this P-Core architecture is an enhanced version of Lion Cove. Just like how Redwood Cove (MTL) is a modified variant of Raptor Cove (RPL).

Nova Lake, the Architecture to Rule Them All

Nova Lake is the holy grail of all Intel things efficient and performant. These CPUs will indeed feature RUs, though we aren’t sure of the P-Core architecture yet. What we are sure of is the E-Core architecture, ‘Arctic Wolf‘, now that’s a cool name.

As MLID states, this is the fruit of Jim Keller’s efforts with Intel. Nova Lake targets a 20-40% single core uplift over Arrow Lake which is very much doable. The top variants feature 180MB/144MB of LLC, we’re not sure if this is Adamantine (L4) or stacked L3 tiles.

Lastly, should Intel’s foundry catch up to TSMC, Nova Lake will debut using the Intel-18A-next node. On the off chance it doesn’t, TSMC’s N2P is the equivalent Intel will seek.

Source: MLID

The post Intel Panther Lake Will Be for Laptops Only, Next Major Desktop Architecture After Arrow Lake, Nova Lake, to Arrive in H2 2026 appeared first on Appuals.com.

Google has introduced a continuous electrodermal activity (CEDA) sensor in the Pixel Watch 2. This sensor tracks the electrical conductivity of your skin, which can be used to measure your body’s response to stress.

Google says that the CEDA sensor can be used to track a variety of metrics, including stress levels throughout the day and identify activities that are causing you stress.

Other than that, the Watch 2 also features a number of other new health and fitness tracking features, such as an upgraded heart rate sensor that is now a multi-path sensor compared to a single-path version.

It can now take readings from multiple spots on your wrist for greater accuracy, and Google says it’s up to 40% more accurate in vigorous activities like HIIT, spinning and rowing. There’s also a new skin temperature sensor that will deliver “better insights” into your sleep and wellness.

The Pixel Watch 2 starts at $350 for the GPS version and $399 for the LTE model. The color options include white, black, gold, silver, blue and hazel. The watch is available to pre-order now, and will start shipping October 12th.

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Strix Point Details Emerge: N4P, 4x More AI Inference Power & Extremely Fast LPDDR5X-8533 Memory

The tweet confirms most of the things we already knew thanks to a huge leak by MLID. For starters, Strix is the successor to the current-generation Phoenix APUs. Strix makes use of a hybrid design hosting 4 Zen5 Cores and 8 Zen5C cores, with 4MB of L2 Cache for the P-Cores and 8MB of L2 Cache for the E-Cores.

The L3 size was debated for a while, however, this rumor alleges that Strix will ship with 2 CCXs, each packing 16MB of L3 Cache. This is slightly different than MLID’s leaked 24MB cache size, but configurations change all the time. The iGPU uses a modified RDNA3 architecture (RDNA3+) with 16 Compute Units (8 WGPs).

Strix will be built using TSMC’s N4P process, coming in at 225mm², ~26% larger than Phoenix. AMD seems to double down on on-chip AI Engine design, offering 4x more AIE-ML Tiles than last-gen. This, mind you, is no small change and can double or even triple performance in AI Inference workloads, making Strix fiercely competitive against Meteor Lake.

There is also support for fast DDR5-5600 memory, or blazing fast ‘soldered’ LPDDR5X-8533 DIMMs. The iGPU directly feeds off the main memory, so the faster the RAM, the faster the iGPU. However, soldered options only go so far as you’ll have to bear a lot of trouble if you wish to increase your memory capacity.

When Does it Launch?

Strix Point is currently scheduled for Q2 or Q3 2024, in line with Intel’s plans for Arrow Lake. Do note that Strix’s actual team-blue equivalent will be Lunar Lake, which should arrive during the same time frame. Both giants are investing heavily in the laptop space, with each generation far more efficient than the last.

If Strix Point and Lunar Lake launch during the same time period, which one would you prefer? Tell us in the comments.

Source: All The Watts

The post AMD Strix Monolithic Uses TSMC N4P & Spans Across 225mm², Features 4x More AIE-ML Tiles & Support for LPDDR5X-8533 Memory appeared first on Appuals.com.

Zen5 ‘Nirvana’ IPC Gains & Design

First off, MLID shared a microarchitecture schematic of Zen5. We will not delve into this, however, chip analyzers on Twitter are probably going to have a field day. MLID states that the new design overhaul should allow for better performance at lower clock speeds, which is beneficial for APUs.

An old roadmap shows that AMD initially expected an IPC uplift of 10-15% from Zen4 to Zen5. We should remind users that AMD is rather conservative regarding their estimates, so the actual IPC uplift may be as high as 20%.

Interestingly, there is a ‘NEW 16 core complex‘ listing which should refer to Zen5c CCDs. It is very much possible that AMD could introduce efficient cores for mainstream desktop consumers.

IPC as a metric, is vague and is often an average of various benchmarks. Whatever IPC AMD mentions when Zen5 launches, through their extensive testing, should be in the ballpark of 10-15%, or even 20%. The Zen5 (P-Core) counterparts are rumored to utilize TSMC’s 4nm process, with Zen5c resorting to 3nm.

Theoretically, Zen5 can offer 8 Zen5 and 16 Zen5C (24 Cores), but that’s not confirmed by any means. As for Turin, complying with a previous rumor, the highest-end offering will go up to 128 Zen5 Cores. Similarly, Turin-Dense (Bergamo-Next) will pack 192 Zen5C cores, though 256 Zen5C cores is a possibility as well.

Zen6 ‘Morpheus’, The Biggest Architectural Leap Since Zen2

With Zen2, AMD opted for a significant paradigm transition with the new MCM layout. This was technically an industry-first, allowing AMD to leapfrog Intel with the next iteration, Zen3. Zen6 is no different as it is expected to stack CCDs on top of IODs, for a true 3D Chiplet Design.

Zen6, is at minimum 10% faster in terms of IPC than Zen5. Moreover, it is expected to leverage the 3nm and 2nm processes, which at the time will be bleeding-edge. Zen6 will compete against Panther Lake, which launches in 2025 and uses the 18A node (1.8nm equivalent).

Due to the 3D design, there might be discrepancies in Zen6’s performance uplifts, depending on the workload. Based on Zen6, EPYC Venice will go as high as 256 Zen6 Cores (SP7 Socket) with core counts possibly increased for desktop/laptop. AMD expects Zen6 to hit shelves by the second half of 2025.

Source: MLID

The post AMD Zen5 Leaked to Offer 15% More IPC, Designed Using TSMC 4nm and 3nm Nodes & Planned for Launch in H1 2024 appeared first on Appuals.com.

GB202 Features 192 SMs & A 512-Bit Memory Bus

It is pertinent to note that in Blackwell, the GB20X wildcard is reserved for the consumer GeForce products. In contrast, the GB10X family indicates data-center Blackwell GPUs.

Kopite alleges that GB100 will feature 8 GPCs, within each of which we find 10 TPCs. Assuming each TPC has 2 SMs, this equates to 160 SMs. Likewise, it can be said that each GPC contains 20 SMs. Now if we presume that the 128 CUDA-core count per SM remains constant, GB100 may host 20480 CUDA/FP32 cores.

Furthermore, GB202, the more mainstream centric die is leaked to ship with 12 GPCs. Each GPC has 8 TPCs and each TPC should have 2 SMs. This sums up to 192 SMs (12 GPCs x 8 TPCs x 2 SMs) or 24576 CUDA cores. Regular readers will know that this is in line with what panzerlied revealed a while back.

In the same thread, Kopite reports that GB100 and GB202 will include a 8192-bit and a 512-bit memory bus respectively. The latter is of greater importance as it coincides with multiple sources. Should NVIDIA resort to GDDR7, the 512-bit interface allows for 48GB of memory and a bandwidth of up to 2 TB/s. More on that here.

• GB100 (Data Center) = 160 SMs | 20480 CUDA Cores | 8192-bit Memory Bus
• GB202 (Gaming) = 192 SMs | 24576 CUDA Cores | 512-bit Memory Bus | 48GB of G7 Memory

Performance & Release Date

Since neither of the aforementioned chips has been taped out yet, it is very difficult to determine the performance. Initial leaks tout the RTX 5090 as up to 1.7x faster than the RTX 4090, the verification of which is not possible.

As for the release date, a leaked roadmap suggests that the RTX 50 series is slated to arrive in early 2025. On the flip side, we have heard from multiple other sources that Blackwell may launch sooner than 2025. Expect more accurate leaks and rumors in 2024, when the chips are likely to enter production.

Source: Kopite

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Ryan Shrout Says Goodbye to Intel

Over a longstanding journey of 5 years, Ryan played an integral role in the Arc division. Alongside the likes of Raja Koduri and Tom Peterson, we would often see Ryan Shrout detailing and delving into the building blocks of Arc’s underlying architecture.

Likewise, it can be said that Ryan’s role was essential to Arc, given how the project suffered many ups and downs. Moreover, Ryan seldom wrote articles pertaining to Intel Arc and would showcase new and improved drivers and features in the form of benchmarks.

The 25th of September marked Ryan’s last day at Intel. He has announced to spend the next couple of weeks with his family, unveiling future plans at a later date. 

Scott Herkleman Follows Suit

Coincidentally, over at Team Red, Scott Herkleman, the Chief of AMD Radeon announced his departure just yesterday. This chain of events will very likely upset both giants. Rubbing salt into the wound, Raja Koduri, Chief Architect and Executive Vice President of Intel’s graphics division also parted ways with Intel early this year.

Intel’s GPU department saw many talented faces come and go. All these major contributors were vital to designing Intel’s first modern GPU architecture. These efforts have laid down foundation for forthcoming generations; Battlemage being one of them.

It will be exciting to see whoever replaces Ryan Shrout and how both companies respond to these sudden changes. 

Source: Ryan Shrout

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Tom’s Hardware had a small Q/A Session with Pat Gelsinger at the Innovation Event. During the conversation, Intel effectively confirmed that it plans to develop 3D Cache Stacking tech somewhere in the future. This can not only be leveraged by Intel’s own CPUs but also by third-party fabless chip-makers if they choose to use Intel silicon.

Intel’s 3D Cache Stacking Tech to Rival AMD & TSMC

With Meteor Lake, Intel has stepped forth into the realm of 3D Packaging. Intel likes to call their approach ‘Foveros‘, and their chiplets ‘Tiles‘. Keeping this in mind, Tom’s Hardware directly asked Pat if Intel had any plans for a 3D V-Cache-like design.

It is very interesting that Pat was upfront regarding this and remarked that Intel does have future products that may integrate 3D Stacked Cache. Here is Pat’s response:

“When you reference V-Cache, you’re talking about a very specific technology that TSMC does with some of its customers as well. Obviously, we’re doing that differently in our composition, right? And that particular type of technology isn’t something that’s part of Meteor Lake, but in our roadmap, you’re seeing the idea of 3D silicon where we’ll have cache on one die, and we’ll have CPU compute on the stacked die on top of it, and obviously using EMIB that Foveros we’ll be able to compose different capabilities.”

Pat Gelsinger

The statement indicates that Intel will not just stack the cache tile over its Compute Tiles like AMD. Rather, Intel aims to put cache-equipped tiles on top of a possible base-tile and stack Compute Tiles on top. If we interpret this a bit further, Intel might stack multiple cache tiles with multiple Compute Tiles.

3D Stacking for All IFS Customers

The concept of 3D Cache Stacking is not exclusive to AMD and is actually offered by TSMC’s SoIC packaging technology. Intel can also use the same 3D Cache design, provided their silicon packaging is versatile enough.

If a client requires as such, Intel can integrate 3D Cache technology into their chips. The CEO has expressed serious confidence in the company’s ability, both as a CPU maker and as a Foundry Service to employ 3D Tile Stacking.

“We feel very good that we have advanced capabilities for next-generation memory architectures, advantages for 3D stacking, for both little die, as well as for very big packages for AI and high-performance servers as well. So we have a full breadth of those technologies. We’ll be using those for our products, as well as presenting it to the Foundry (IFS) customers as well,” 

Pat Gelsinger

Moreover, future Xeons can go cache-dense and compete against their respective AMD counterparts. It is very important to note that Pat explicitly states Intel has 3D-Cache products scheduled in their roadmap.

The inclusion of vertically stacked cache in AMD’s mainstream Ryzen lineup has led to insanely efficient CPUs. All X3D CPUs are not just fast (in certain workloads) but also very power conservative. Under proper conditions, V-Cache acts as AMD’s trump card because the 7800X3D can sometimes easily eclipse both flagship Intel Core and Ryzen CPUs.

Source: Tom’s Hardware

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The i5-14400 Might Feature Two Different Variations

Today’s leak sources from bilibili tipster, ECSM who shared two different CPU-Z images of the i5-14400. The only visible difference between the two is the stepping. While that might not appeal to many, it shows that Intel is still keen on using Alder Lake silicon, two generations later. Here’s why:

Last year, Appuals released a full-fledged article detailing and benchmarking Intel’s i5-13400, weeks before launch. More on that here. We noticed something peculiar regarding the 13400 in the sense that our C0 model was based on Alder Lake (a binned down i5-12600K).

This was further verified when users spotted different i5-13400 variations. The B0 stepping would feature the new ‘Raptor Cove‘ P-Cores whereas the majority would be stuck with C0 revisions, which coincidentally used ‘Golden Cove’ P-Cores.

Now it is not confirmed that the same will carry over to Raptor Lake Refresh as well. Though since all 3 architectures (ADL, RPL, RPL-R) are kind of similar, that might just be the case. The only confirmation will be when these CPUs hit the shelves.

Will There be Any Performance Penalties?

The short answer is, probably not. When Raptor Lake launched, Intel likely had a lot of left-over Alder Lake dies. It made sense to re-use the same dies because the IPC difference between Raptor Cove and Golden Cove is just 1.4%. Besides, as Alder Lake is now probably low in inventory, Intel might predominantly switch to Raptor Cove for the 14400.

The difference between the 13400 (Raptor Cove) and the 13400 (Golden Cove) is probably not that major. Both Alder Lake and Raptor Lake utilize the same underlying architecture whereas Raptor Cove is hardly faster than its predecessor. The ‘huge’ generational leap you see on the Raptor Lake K-SKUs is primarily due to the increased clocks and 2x more cache per each e-core cluster.

i5-13400 (C0) vs i5-13400 (B0)

Again, the only way to know which dies are being used the most will be at launch. Intel adopts this strategy to improve yields and clear away remaining stock. The budget Non-K 65W Raptor Lake Refresh lineup is planned for CES 2024. Stay tuned at Appuals for more articles like this.

Source: ECSM (bilibili)

The post The ’14th Gen’ Intel i5-14400 May be Based on Alder Lake ‘C0’ or Raptor Lake ‘B0’ appeared first on Appuals.com.

We initially expected this to be a small reveal of Meteor Lake and Raptor Lake Refresh. However, Intel has stepped things by and brought to light so many new products and wafers, that we cannot neglect their importance.

Intel 3, 20A & 18A Wafers Smile for the Camera

For the unaware, Meteor Lake is fabricated using Intel’s latest 4nm-class ‘Intel 4‘ node. Future Xeons will make use of Intel 3. As we go up the stack, Intel 20A (2nm) is planned for Arrow Lake launching next year. Moreover, we also got to see a glimpse of 18A, powering Panther Lake, scheduled for 2025.

Intel 3, used by Granite Rapids and Sierra Forest was displayed in its wafer form. Pat Gelsinger, CEO Intel, claims that Granite Rapids can offer 2.4x more efficiency than the current-gen Xeons. Granite Rapids is tipped to ship with 132 P-Cores, split across 3 dies.

Furthermore, Sierra Forest will arrive in 96-core, 128-core and 144-core flavors. With two dies fused on a single package, Intel has formed a 288-core SKU as well. This product will give some serious competition to AMD’s Bergamo which uses Zen4C efficiency cores.

‘Intel 20A‘, the company’s 2nm-equivalent node was also showcased. This process node is reserved for Arrow Lake which is inbound next year.

Last but not least, we set our eyes on a true beauty, Intel’s very own 18A process (1.8nm). This is merely a test chip and is unable for use in any product, for now. 18A is slated to arrive in 2025 with Panther Lake.

Panther Lake in 2025

The giant officially disclosed that Panther Lake will launch after the mobile-only Lunar Lake in 2025. Importantly, Panther Lake, as stated above is designed using the 18A process. We are not sure if Panther Lake is planned for both desktop and mobile, but Intel should confirm that as we inch closer to its launch.

Glass & Quantum Wafers

Showcasing Intel’s latest developments and breakthroughs ins the packaging field, Pat displayed a few very interesting wafers. 25 years ago, Intel defined the basis of our modern-day package, using an organic substrate.

Below is a Glass Wafer, one that Intel unveiled just yesterday. Glass wafers offer a plethora of advantages over traditional organic packages. This is the result of a decade’s worth of research and glass packaging is en route for 2030.

Next-up, we have a 12 Qubit wafer that powers Intel’s ‘Tunnel Falls‘ quantum products. Intel has achieved a remarkably high 95% yield rate. Due to the small size of these devices, coming in at just 50nm x 50nm, they are ~1 Million times smaller than your average chip.

Moreover, these chips operate between 1 and 0 Kelvin (-273* Celsius). It will take Intel some serious cryogenic wizardry to get these chips to work, but the concept is enticing.

Conclusion

Despite many setbacks, Intel is keen on delivering its promise of 5 nodes in 4 years. The company’s announcements today were extremely exciting, though a bit unexpected. Likewise, Team Blue is now following a 1-year cadence between its CPU architectures, and even nodes in some cases.

Between 2023–25, the company will see a shift from Intel 7 (7nm) to Intel 18A (1.8nm). Which future Intel products are you the most excited about? Tell us in the comments below.

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